1. Field of the Invention
This invention pertains generally to chip-to-chip communications, and more particularly to a self tracking serializer de-serializer.
2. Description of Related Art
Conventional serializer de-serializer I/O is based on multiplexing and demultiplexing digital communications. Using such conventional schemes to increase communications bandwidth requires increasing clock rate.
Attempting to use multi-frequency bands in a traditional scheme for modulation and demodulation to overcome the above problems brings up additional issues. Current multi-frequency serializers and de-serializers for use with chip-to-chip I/O include modulation and demodulation that are complicated and dependent on external factors, such as silicon process, connection conditions, power supply quality, and the like. In these conventional systems, a complicated scheme, such as error correction or base band processing is required to achieve reliable modulation and demodulation with low bit error rate. When the latency of modulation and demodulation becomes critical in the I/O connection, the traditional base band processing, used to ensure low bit-error-rate (BER), in modulation and demodulation becomes impractical.
The use of base band processing techniques can in some cases provide for reliable data transmission and reception, yet it comes with a high cost penalty regarding circuit complexity and unnecessarily long delays for data processing. Although the typical multi-frequency approach may be suitable for high throughput operations, it is not well suited when short latencies are required to perform mission critical operations.
Accordingly, a need exists for chip-to-chip multi-frequency communication circuits that have short latencies and are readily implemented. The present invention fulfills these needs, and overcomes shortcomings of previous multi-frequency chip-to-chip communication topologies.